Memory modules are well known to the prior art and have been and are presently being used in practical applications such as in computers and other equipment using solid state memories.
Broadly speaking, currently available main memories offer bandwidths in the range of 1.6 to 2.6 GB/s, and although some memories provide for limited data path error correction most offer no means of any error correction. Furthermore, memory modules for server products usually include redrive logic for address and command inputs, and clock re-synchronization and redrive circuitry to ensure accurate clock timings at each device on the memory assembly. Although these solutions provide systems with the ability to achieve the specified bandwidth objectives, the overall quantity and types of failures in the memory subsystem, outside the data path itself, has actually increased due to the added circuitry associated with each memory device. Simultaneously, as servers are more widely utilized in business, many server applications simply cannot accept periodic unplanned system outages caused by failed memory modules. Thus the emphasis and need of improved overall system reliability is increasing dramatically and requires a comprehensive system solution that includes both a high degree of fault tolerance and overall reliability.
The present invention provides such a comprehensive system solution that includes the high degree of fault tolerance and the overall differentiated system reliability long desired in the server market.
Other possible solutions, such as memory mirroring, symbol slicing and extensive forms of fault rejection and redundancy, provide enhanced memory subsystem reliability, but, due to negative impacts such as increased cost, power, and reduced performance, have been considered only for niche applications where price is not of high importance as these subsystem quality enhancements are very expensive to implement. Therefore solutions suitable for the low or midrange server markets have not been available.
Consequently the industry has long sought a simple, relatively inexpensive and reliable solution that provides differentiated product quality, that provides an adequate level of asset-protection that does not endanger the reliability of the system through the use of reduced-function memory assemblies and yet is cost competitive.